1. Field of the Invention
The present invention generally relates to a non-volatile memory, and more particularly to a method for forming the self-aligned buried N+ type to diffusion process in ETOX flash cell.
2. Description of the Prior Art
Flash memory is the most potential memory in the semiconductor industry. Flash memory has been broadly applied to repeatedly access data and to remain assessable during power break down, such as the film of digital camera or the basic input-output system of a motherboard. Because flash memory has the advantages of electrically erasable and programmable, it can simultaneously proceed the erase and the program mechanisms to all flash memory cells in the whole memory array. Accordingly, how to advance the performance and reduce the cost of the flash memory became an important subject.
High-density flash memories have been developed as file memories in portable equipment such as hand-held computer and digital still cameras. One of the most important issues for the memory is low bit cost by reducing cell size. To reduce the cell size, the data line pitch as well as the gate length must be reduced. We have report 0.4 xcexcm2 contactless-array memory cells, with 3 feature size data-line pitch, using self-aligned isolation. However, the smaller data-line pitch causes a higher internal operating voltage because the coupling ratio decreases due to the decrease in the surface area of floating gates. Therefor, the isolation breakdown voltage should be maintained even through the isolation region is reduced. Moreover, a cell with a high coupling ratio resulting from increasing inter-poly capacitance is necessary to reduce the operating voltage.
Referring to FIG. 1A, a substrate 100 is provided, and the substrate 100 comprises silicon. Then, a pad oxide layer 102 is formed on the substrate 100. The pad oxide 102 is formed by using a thermal oxide method. Next, a dielectric layer 104 is formed on the pad oxide layer 102. The dielectric layer 104 comprises silicon nitride. The dielectric layer 104 is formed by using a chemical vapor deposition method. Then, a portion of the dielectric layer 104, pad oxide layer 102 and the substrate 100 are etched to form a shallow trench isolation openings 105 in the substrate 100.
Referring to FIG. 1B, a silicon oxide is filled up the shallow trench isolation openings 105. Next, the shallow trench isolation openings 105 are planarized to form a shallow trench isolation 106 by using a chemical mechanical polishing method. Then, the dielectric layer 104 is removed on the pad oxide layer 102.
Referring to FIG. 1C, a diffusion pattern mask 109 is formed pad oxide layer 102. Then, the burried N+-type ions are implanted 10 into the substrate 100 to form a source/drain region 110. The source/drain region 110 is not symmetric cell. The non self-aligned method has a fatal drawback that alignment accuracy will affect cell symmetry and bit/source line resistance.
For the forgoing reasons, there is a necessity for a method for forming the self-aligned buried N+-type to diffusion process in ETOX flash cell. This invention provided a method to fabricate symmetric cell and much stable bit/source line resistance.
In accordance with the present invention is provided to a method for forming the self-aligned buried N+-type to diffusion process in ETOX flash cell to provide symmetric cell and much more sable bit/source line resistance.
One object of the present invention is to provide a method for forming the self-aligned buried N+-type to diffusion process in ETOX flash cell and also to fabricate symmetric cell for ETOX flash cell operation.
Another object of the present invention is to provide a method for forming the self-aligned buried N+ type to diffusion process in ETOX flash cell to stable bit/source line resistance.
In order to achieve the above objects, the present invention provides a method for forming the self-aligned buried N+-type to diffusion process in ETOX flash cell. First of all, a substrate is provided having a pad oxide layer thereon, a dielectric layer on the pad oxide layer, and a cap layer on the dielectric layer. Then, a portion of the cap layer and the dielectric layer are etched to stop on the pad oxide layer to define an active region. Then, a spacer is formed on sidewall of the dielectric layer. Next, a portion of the pad oxide layer and the substrate are etched through said buried N+-type region to form a opening in the substrate. Finally, a field oxide region is formed in the substrate.